1. Field of the Invention
The present invention relates to a testing of an large scale integrated (LSI) semiconductor circuit mainly comprising a complementary Metal Oxide Semiconductor (CMOS) circuit, and it particularly relates to a d.c. current reduction circuit utilized for a testing which is capable of accurately detecting a diminutive defect within a semiconductor chip.
2. Description of the Prior Art
In a conventional CMOS circuit configured in a complementary manner to combine a PMOS element and an NMOS element, there is presented a circuit structure such that a current path between the VDD side of a high potential of a power supply and the VSS side of a low (or ground) potential is shut off, so that it is known that a very small amount of a leak current (referred to as a standby current hereinafter) flows as shown in FIG. 2., that is, a two-input CMOS NAND where an input thereof and an output thereof are stabilized. For example in this connection, such the standby current is only some to tens of some nA's in a VLSI having one million or more transistors under a design rule of 1.0 .mu.m at a room temperature. Such current value range remains the same order regardless of any input values.
On the other hand, when there exists even a slight deficiency in the LSI chip constructed by the CMOS circuit, the standby current abnormally increases from a normal case thereof, so that such the defficiency can be easily detected and distinguished from a nondefective. It is rather difficult to detect such the small deficiency by a normal function test, or a test based on design for testability such as a scan test, bulit-in self-test or the like where a circuit in question is evaluated merely by a logical value of an output from a circuit block to be tested.
However, since these defeciencies seem to really appear as an output value error with a high probability as a result of deterioration due to long-term usage thereof, such the deficient chips are desirable to be evaluated as such at the time of delivery thereof so as not be delivered to a product market at all. Accordingly, there is implemented a standby current test for selecting whether a chip is nondefective or not. In the near future, minuteness of a production process of a chip seems to get into a submicron area and, therefore, contributory factors for causing the small leak current described above may substantially increase. Thus, importance of the standby current test is anticipated to increase as well which is capable of detecting small deficiencies existing inside the chip.
Now, by observing generally and carefully LSI circuits constituted by the CMOS circuits, it is easily recognized that there are not many LSI's constituted solely by CMOS circuits. In a case where the circuit is intended to have a less area or is designed to have a high-speed operation therefor, there are oftentimes used (1) a ratio type circuit and (2) a precharged type circuit.
Referring to FIG. 9A, there is shown an example of the ratio type circuit (1). In the same figure, a node 1 which operates in a ratio type manner is connected to an inverter 3 as an input. Then, an output thereof becomes an output Z of this ratio type circuit. A PMOS element 2 which serves to supply a charge from the VDD power supply is grounded at its gate input, so that the PMOS element 2 is constantly in a state of ON. A potential of the node 1 is determined by inputs I.sub.1 through I.sub.n. When the potential of these inputs are all equal to VSS whose logic is 0 (referred simply to 0 hereinafter), the potential of the node 1 is VDD whose logic is 1 (referred simply to 0 hereinafter), and the potential of output Z becomes VSS.
On the other hand, when the potential of any input among I.sub.1 through I.sub.n becomes VDD, corresponding one of NMOS devices 6.sub.1 through 6.sub.3 becomes ON. Since a resistance (ON resistance) of the PMOS device 2, while the PMOS device 2 is ON, is designed to be sufficiently higher than that of the NMOS device, the potential of node 1 is sufficiently lower than the logic threshold value of the inverter 3. As a consequence thereof, the potential of output Z becomes VDD.
The ratio type circuit shown in FIG. 9A is a logic sum circuit whose inputs are I.sub.1, I.sub.2, . . . , I.sub.n (in Boolean expression, I.sub.1 +I.sub.2 + . . . + I.sub.n). In order for the d.c. current not to flow in this circuit, every input potential need be set at VSS, in other words, there is, in most cases, formed a current path from VDD node toward VSS node unless there is a special condition set forth on input combination thereof. Moreover, in these cases, the input of the inverter 3 is not exactly equal to VSS, so that there is formed a d.c. current path in the inverter 3. Therefore, in most input combinations it is almost impossible to detect the small amount of current change in terms of CMOS.
Referring to FIG. 9B, there is shown an example of the precharged type circuit (2). In FIG. 9B, the same numbered parts are identical to those shown in FIG. 9A.
Referring to FIG. 9B, when a clock signal is equal to 1 (CLK=1) (i.e. during precharging), the PMOS element 2 and NMOS element 4 are ON. Then, the node 1 is connected to the power supply (potential Vdd) and NMOS elements 6.sub.4 through 6.sub.6 are in the state of OFF. Therefore, the node 1 is precharged up to VDD, regardless of values of input I.sub.1, I.sub.2, . . . , I.sub.n.
Still referring to FIG. 9B, The NMOS elements 6.sub.4 through 6.sub.6 serve to suppress a power dissipation by preventing a d.c. current from flowing during the precharging. In a case where such NMOS elements are not required so that a high-speed operation can be achieved, such NMOS elements may not be implemented at all. Though the NMOS element 4 is such that the node 1 is usually precharged up to the potential of (VDD-Vth,n) (where Vth,n denotes a threshold voltage of the NMOS 4), the NMOS 4 can generally perform precharging faster than PMOS element, thus PMOS element being implemented. In this connection, if there is sufficient time allowed until the precharging is completed, there may be utilized the PMOS element 2 alone. On the contrary, there is a case where it suffices to precharge up to the potential of (VDD-Vth,n), and, in this case, the NMOS element 4 alone may be sufficient.
Notice that, hereinafter, a circuit supplying the electric charge to the node from the power supply (potential VDD) will be expressed and denoted by the reference number 100, the node being connected either in the ratio type or the precharge type operation.
Next, when the clock equals to 0 (CLK=0, i.e. during operation), NMOS elements 6.sub.4 through 6.sub.6 are ON. Thus, the output of this precharged circuit is determined responsive to inputs I.sub.1, I.sub.2, . . . , I.sub.n. When any one of these inputs is 1, such a corresponding NMOS element, among 61 through 63, becomes ON. Consequently, the electric charge of node 1 is discharged and the logic value thereof becomes 0, thus the output Z being equal to 1.
On the other hand, when every input is 0, every NMOS element (6.sub.1 through 6.sub.3) becomes OFF. Then, the electric charge corresponding to 1 shall be maintained while the node 1 is not connected to the power supply (potential VDD). In this case, the potential of the circuit will change to the value between VDD and VSS as time lapses-due to a leak current thereof. Therefore, a circuit such as an inverter which receives this node as a gate input, becomes weakly ON. As a result thereof, a d.c. current will flow through, so that the small amount of the current is very difficult to be observed in CMOS circuit under a stable state.
As described above, during the precharging, the d.c. current flows through the usual precharge type circuit having therein MOS elements such as 6.sub.4 through 6.sub.6 which serve to shut off the d.c current path, so that the standby current test can be executed. However, during operation, similar to the ratio type circuit, there is a case where the standby current test can not be executed depending on the input combination. In a particular case where the NMOS elements are serially connected in which I.sub.1 through I.sub.n serve as a gate input, such the standby current test can not be executed for almost every input combination which makes the precharged node unconnected to either power supply.
Notice that, in each ratio type and precharged type circuit, there exist two types: one is that an objective node is connected to VDD side of the power supply so as to supply the electric charge; other is that the objective node is connected to VSS side of the power supply so as to discharge the electric charge.
Accordingly, in the LSI circuits mainly comprising the CMOS circuit including therein some ratio type and precharged type circuits, there exists a strong possibility that the d.c. current may flow unwantedly under the stable state thereof against almost every input combination, so that an effective standby current test can not be executed. On the other hand, as described above, understood is advantageous aspects in the conventional CMOS related LSI circuits, and such the conventional circuits have sometimes been utilized. Now, a basic concept in the conventional manner lies in that there are arranged the ratio type and precharged type circuits so as not to interfere the standby current test. For further detail thereof, there are shown some conventional practices below.
Referring to FIG. 1, there is shown a conventional example of the ratio type circuit. In addition to the inputs I.sub.1, . . . , I.sub.n in which output z is supplied in a similar way with a normal operation according to the circuit shown in FIG. 9A, the ratio type circuit of FIG. 1 is controlled by input signal S.sub.1. In the ratio type circuit shown in FIG. 1, NMOS elements are connected such that output Z=I.sub.1 +I.sub.2 .multidot.(I.sub.3 +I.sub.4)+ . . . . + I.sub.n. The input signal S.sub.1 controls to switch (ON/OFF) the PMOS element 2, which was on the contrary constantly ON in FIG. 9A. Moreover, the input switch S.sub.1 controls to switch the NMOS element 70 which is connected between the output node 1 and VSS.
When the input signal S.sub.1 is equal to zero (S.sub.1 =0), the PMOS element 2 is ON and the NMOS element 70 is OFF. Therefore, the ratio type circuit of FIG. 1 operates normally, in other words, the ratio type circuit of FIG. 1 operates same as in the circuit of FIG. 9A. On the other hand, when S.sub.1 is equal to one (S.sub.1 =1), the PMOS element 2 is OFF which supplies the electric charge to the output node 1 from the power supply (potential VDD) and the NMOS element 70 becomes ON. Consequently, node 1 is fixed to 0 and output Z is thus fixed to 1 (Z=1).
Accordingly, the d.c. current path is shut off at the input signal S1=1, so that the ratio type circuit of FIG. 1 does not detrimentally affect the standby current test of a whole semiconductor chip. As for the precharged circuit, the circuit configuration thereof is designed such that the d.c. current does not flow therethrough during the precharging under normal implementation thereof. Therefore, the standby current test may best be executed during such the precharging. For example, output Z=0 in FIG. 9B.
However, in the conventional practice above mentioned, the standby current test is performed under a state in which the output of the respective ratio type and precharged type circuits is fixed to a certain logic value. Now, in a recent and future trend where a production process for the semiconductor chip enters into a submicron order, there is anticipated that the deficiency accompanied by the small amount of leak current is likely to occur. Therefore, in order to guarantee and secure a long-term reliability of the LSI chips to be delivered to the market, it is indispensable that any slight deficiency in each semiconductor element inside the LSI circuits be detected without fail.
However, in the conventional method in which the fixed value can only be output, each node value inside the LSI circuits can not be set at any possible value, so that an evaluation thereby can only end up incomplete against detecting the slight deficiency in such nodes. Therefore, there have been a great demand for an effective standby current test replacing the conventional practice. As described so far, in the conventional test for LSI circuits mainly comprising CMOS circuits, though the standby current test is carried out which detects the slight deficiency by way of observing the small amount of change in the leak current, the fixed values are output in case of testing the CMOS circuits including the ratio type and precharge type circuits and thus it is hard to carry out such a test sufficiently enough under the conventional practice.